831752AGILF集成电路（IC）的时钟缓冲器驱动器规格书PDF中文资料

Features

• Clock switch for PCIe and ATCA/AMC applications

• Supports local and common ATCA/AMC clock modes

• Bi-directional clock I/O FCLK:

- When operating as an output, FCLK is a source-terminated

HCSL signal.

- When operating as an input, FCLK accepts HCSL, LVDS and

LVPECL levels.

• Local clock input (CLK) accepts HCSL, LVDS and LVPECL

differential signals

• Local HCSL clock output (Q)

• Maximum input/output clock frequency: 500MHz

• Maximum input/output data rate: 1000Mb/s (NRZ)

• LVCMOS interface levels for the control inputs

• PCI Express (2.5 Gb/S), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) jitter

compliant

• Full 3.3V or 2.5V supply voltage

• Lead-free (RoHS 6) 16-lead TSSOP package

• -40°C to 85°C ambient operating temperature