1-to-1 2.5V, 3.3V Differential-to-LVCMOS/LVTTL Translator

General Description 830s21I is a 1-to-1 Differential-to- LVCMOS/ LVTTL translator and a member of the family of High Performance Clock Solutions from IDT. The differential input is highly flexible and can accept the following input types: LVPECL, LVDS, LVHSTL, SSTL and HCSL. The small 8-lead

文件：547.58 Kbytes 页数：13 Pages

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Differential-to-LVCMOS/LVTTL Translator

文件：354.69 Kbytes 页数：12 Pages

IDT

1-to-1 2.5V, 3.3V Differential-to-LVCMOS/LVTTL Translator

General Description 830S21I-01 is a 1-to-1 Differential-to- LVCMOS/ LVTTL translator and a member of the family of High Performance Clock Solutions from IDT. The differential input is highly flexible and can accept the following input types: LVPECL, LVDS, LVHSTL, SSTL and HCSL. The small 8-le

文件：548.45 Kbytes 页数：13 Pages

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Differential-to-LVCMOS/LVTTL Translator

文件：355.52 Kbytes 页数：12 Pages

IDT

1-to-1,2.5V,3.3V Differential-to-LVCMOS/LVTTL Translator

830S21I is a 1-to-1 Differential-to- LVCMOS/ LVTTL translator and a member of the family of High Performance Clock Solutions from IDT. The differential input is highly flexible and can accept the following input types: LVPECL, LVDS, LVHSTL, SSTL and HCSL. The small 8-lead SOIC footprint makes this d One LVCMOS/LVTTL output\nDifferential CLK, nCLK input pair\nCLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL\nMaximum output frequency: 350MHz\nPart-to-part skew: 525ps (maximum)\nAdditive Phase jitter, RMS: 0.11ps (typical)\nSmall 8 lead SOIC packa;

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1-to-1,2.5V,3.3V Differential-to-LVCMOS/LVTTL Translator

830S21I-01 is a 1-to-1 Differential-to- LVCMOS/ LVTTL translator and a member of the family of High Performance Clock Solutions from IDT. The differential input is highly flexible and can accept the following input types: LVPECL, LVDS, LVHSTL, SSTL and HCSL. The small 8-lead SOIC footprint makes thi One LVCMOS/LVTTL output\nDifferential CLK, nCLK input pair\nCLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL\nMaximum output frequency: 350MHz\nPart-to-part skew: 525ps (maximum)\nAdditive phase jitter, RMS: 0.11ps (typical)\nSmall 8 lead SOIC packa;

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