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83026I

Low Skew, 1-to-2, Differential-to-LVCMOS/LVTTL Fanout

Features • Two LVCMOS/LVTTL outputs • Differential CLK/nCLK input pair • CLK/nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency: 350MHz (typical) • Output skew: 20ps (maximum) • Part-to-part skew: 600ps (maximum) • Additive pha

文件:504.22 Kbytes 页数:13 Pages

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83026I

Differential-to-LVCMOS/LVTTL Fanout

文件:311.31 Kbytes 页数:12 Pages

IDT

83026I-01

Low Skew, 1-to-2 Differential-to-LVCMOS/LVTTL Fanout Buffer

FEATURES • Two LVCMOS / LVTTL outputs • Differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 350MHz • Output skew: 15ps (maximum) • Part-to-part skew: 600ps (maximum) • Additive p

文件:372.16 Kbytes 页数:16 Pages

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83026I-01

Differential-to-LVCMOS/LVTTL Fanout Buffer

文件:176.4 Kbytes 页数:15 Pages

IDT

83026I

Low Skew,1-to-2,Differential-to-LVCMOS/LVTTL Fanout Buffer

The 83026I is a low skew, 1-to-2 Differential-to- LVCMOS/LVTTL Fanout Buffer and a member of the family of High Performance Clock Solutions from IDT.The differential input can accept most differential signal types (LVDS, LVHSTL, LVPECL, SSTL, and HCSL) and translate to two single-ended LVCMOS/LVTTL ·Two LVCMOS/LVTTL outputs\n·Differential CLK/nCLK input pair\n·CLK/nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL\n·Output frequency: 350MHz (typical)\n·Output skew: 20ps (maximum)\n·Part-to-part skew: 600ps (maximum)\n·Additive phase jitter, RMS: 0.09;

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83026I-01

Low Skew,1-to-2 Differential-to-LVCMOS/LVTTL Fanout Buffer

The 83026I-01 is a low skew, 1-to-2 Differential-to- LVCMOS/LVTTL Fanout Buffer. The differential input can accept most differential signal types (LVPECL, LVDS, LVHSTL, HCSL and SSTL) and translate to two singleended LVCMOS/LVTTL outputs. The small 8-lead SOIC footprint makes this device ideal for u Two LVCMOS / LVTTL outputs\nDifferential CLK, nCLK input pair\nCLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL\nMaximum output frequency: 350MHz\nOutput skew: 15ps (maximum)\nPart-to-part skew: 600ps (maximum)\nAdditive phase jitter, RMS: 0.03ps (t;

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供应商型号品牌批号封装库存备注价格
24+
N/A
47000
一级代理-主营优势-实惠价格-不悔选择
询价
Belden
2022+
1
全新原装 货期两周
询价
Belden
22+
NA
10
加我QQ或微信咨询更多详细信息,
询价
MOLEX
1
全新原装 货期两周
询价
更多83026I供应商 更新时间2026-1-7 11:06:00