82V3155中文资料Enhanced T1/E1/OC3 WAN PLL With Dual Reference Inputs数据手册Renesas规格书

描述 Description

The 82V3155 is an enhanced T1/E1/OC3 WAN PLL with dual reference inputs. It contains a Digital Phase-Locked Loop (DPLL), which generates low jitter ST-BUS, 19.44 MHz and 155.52 MHz clock and framing signals that are phase locked to an 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz input reference. The 82V3155 provides 10 types of clock signals (C1.5o, C3o, C6o, C2o, C4o, C8o, C16o, C19o, C32o, C155) and 7 types of framing signals (F0o, F8o, F16o, F19o, F32o, RSP, TSP) for multitrunk T1/E1 and STS3/OC3 links. The 82V3155 is compliant with AT&T TR62411, Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced, Stratum 4, OC-3 port, 155.52 Mbit/s application and ETSI ETS 300 011, ITU-T G.813 Option 1, and ITU-T G.812 Type IV clocks. It meets the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, phase change slope, holdover frequency accuracy and MTIE (Maximum Time Interval Error) requirements for these specifications. The 82V3155 can be used in synchronization and timing control for T1, E1 and OC3 systems, or used as ST-BUS clock and frame pulse source. It also can be used in access switch, access routers, ATM edge switches, wireless base station controllers, or IADs (Integrated Access Devices), PBXs, line cards and SONET/SDH equipments.

特性 Features

Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 clock, OC-3 port and 155.52 Mbit/s application
Supports ITU-T G.813 Option 1 clocks
Supports ITU-T G.812 Type IV clocks
Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface
Selectable reference inputs: 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz
Accepts two independent reference inputs which may have same or different nominal frequencies applied to them
Provides C1.5o, C3o, C2o, C4o, C6o, C8o, C16o, C19o, C32o and C155 output clock signals
Provides 7 types of 8 kHz framing pulses: F0o, F8o, F16o, F19o,F32o, RSP and TSP
Provides a C2/C1.5 output clock signal with the frequency controlled by the selected reference input Fref0 or Fref1
Holdover frequency accuracy of 0.025 ppm
Phase slope of 5 ns per 125 ?s
Attenuates wander from 2.1 Hz
Fast lock mode
Provides Time Interval Error (TIE) correction
MTIE of 600 ns
JTAG boundary scan
Holdover status indication
Freerun status indication
Normal status indication
Lock status indication
Input reference quality indication
3.3 V operation with 5 V tolerant I/O
Package available: 56-pin SSOP (Green option available)