82V2042E数据手册集成电路（IC）的电信规格书PDF

描述 Description

The IDT82V2042E can be configured as a dual channel T1, E1 or J1 Line Interface Unit. The IDT82V2042E performs clock/data recovery, AMI/ B8ZS/HDB3 line decoding and detects and reports the LOS conditions. An integrated Adaptive Equalizer is available to increase the receive sensitivity and enable programming of LOS levels. In transmit path, there is an AMI/ B8ZS/HDB3 encoder and Waveform Shaper. There is one Jitter Attenuator, which can be placed in either the receive path or the transmit path. The Jitter Attenuator can also be disabled. The IDT82V2042E supports both Single Rail and Dual Rail system interfaces. To facilitate the network maintenance, a PRBS/QRSS generation/detection circuit is integrated in the chip, and different types of loopbacks can be set according to the applications. Four different kinds of line terminating impedance, 75 Ω,100 Ω, 110 Ω and 120 Ω are selectable on a per channel basis. The chip also provides driver shortcircuit protection and internal protection diode and supports JTAG boundary scanning. The chip can be controlled by either software or hardware. The IDT82V2042E can be used in LAN, WAN, Routers, Wireless Base Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices, CSU/DSU equipment, etc.

特性 Features

• Dual channel T1/E1/J1 short haul line interfaces
• Supports HPS (Hitless Protection Switching) for 1+1 protection without external relays
• Programmable T1/E1/J1 switchability allowing one bill of material for any line condition
• Single 3.3 V power supply with 5 V tolerance on digital interfaces
• Meets or exceeds specifications in
• ​ANSI T1.102, T1.403 and T1.408
• ITU I.431, G.703, G.736, G.775 and G.823
• ETSI 300-166, 300-233 and TBR12/13
• AT&T Pub 62411