丝印：8101；Package：32LdQFN；Adaptive Digital DC/DC PWM Controller with Auto Compensation

文件：1.57394 Mbytes 页数：36 Pages

RENESAS

瑞萨

丝印：8101；Package：32LdQFN；Adaptive Digital DC/DC PWM Controller with Auto Compensation

文件：1.57394 Mbytes 页数：36 Pages

RENESAS

瑞萨

丝印：8101；Package：32LdQFN；Adaptive Digital DC/DC PWM Controller with Auto Compensation

文件：1.57394 Mbytes 页数：36 Pages

RENESAS

瑞萨

丝印：8101602EA；Package：CDIP；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器

丝印：8101801EA；Package：CDIP；CD405xB CMOS Single 8-Channel Analog Multiplexer or Demultiplexer With Logic-Level Conversion

1 Features • Wide range of digital and analog signal levels: – Digital: 3 V to 20 V – Analog: ≤ 20 VP-P • Low ON resistance, 125 Ω (typical) over 15 VP-P signal input range for VDD – VEE = 18 V • High OFF resistance, channel leakage of ±100 pA (typical) at VDD – VEE = 18 V • Logic-level co

文件：1.72366 Mbytes 页数：48 Pages

TI

德州仪器

丝印：8101801EA；Package：CDIP；CD405xB CMOS Single 8-Channel Analog Multiplexer or Demultiplexer With Logic-Level Conversion

1 Features • Wide range of digital and analog signal levels: – Digital: 3 V to 20 V – Analog: ≤ 20 VP-P • Low ON resistance, 125 Ω (typical) over 15 VP-P signal input range for VDD – VEE = 18 V • High OFF resistance, channel leakage of ±100 pA (typical) at VDD – VEE = 18 V • Logic-level co

文件：1.66329 Mbytes 页数：42 Pages

TI

德州仪器

丝印：8101602EA；Package：CDIP；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器

丝印：8101602EA；Package：CDIP；CMOS Presettable Up/Down Counter

Features: ® Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ® Binary or d

文件：1.02221 Mbytes 页数：22 Pages

TI

德州仪器

丝印：8101701EA；Package：CDIP；CMOS 4-Stage Parallel In/Parallel Out Shift Register

Features: ® 4-Stage clocked shift operation # Synchronous parallel entry on all 4 stages a JK inputs on first stage ® Asynchronous True/Complement control on all outputs ® Static flip-flop operation; Master-slave configuration ® Buffered inputs and outputs ® High speed — 12

文件：710.52 Kbytes 页数：17 Pages

TI

德州仪器

丝印：8101701EA；Package：CDIP；CMOS 4-Stage Parallel In/Parallel Out Shift Register

Features: ® 4-Stage clocked shift operation # Synchronous parallel entry on all 4 stages a JK inputs on first stage ® Asynchronous True/Complement control on all outputs ® Static flip-flop operation; Master-slave configuration ® Buffered inputs and outputs ® High speed — 12

文件：710.52 Kbytes 页数：17 Pages

TI

德州仪器