810001DK-21集成电路（IC）的应用特定时钟/定时规格书PDF中文资料

General Description

The ICS810001-21 is a PLL based synchronous clock generator that is optimized for digital video clock jitter attenuation and frequency translation. The device contains two internal frequency multiplication stages that are cascaded in series.

特性 Features

• Jitter attenuation and frequency translation of video clock signals

• Supports SMPTE 292M, ITU-R Rec. 601/656 and MPEG-transport clocks

• Support of High-Definition (HD) and Standard-Definition (SD) pixel rates

• Dual VCXO-PLL supports both 60 and 59.94Hz base frame rates in one device

• Supports both 1000/1001 and 1001/1000 rate conversions

• Dual PLL mode for high-frequency clock generation (36MHz to 148.5MHz)

• VCXO-PLL mode for low-frequency clock generation (27MHz and 26.973MHz)

• One LVCMOS/LVTTL clock output

• Two selectable LVCMOS/LVTTL clock inputs

• LVCMOS/LVTTL compatible control signals

• RMS phase jitter @148.3516MHz, (12kHz - 20MHz): 1.089ps (typical)

• 3.3V supply voltage

• 0°C to 70°C ambient operating temperature

• Available in both standard (RoHS 5) and lead-free (RoHS 6) packages