810001-21中文资料瑞萨数据手册PDF规格书

General Description

The 810001-21 is a PLL based synchronous clock generator that is

optimized for digital video clock jitter attenuation and frequency

translation. The device contains two internal frequency multiplication

stages that are cascaded in series. The first stage is a VCXO PLL

that is optimized to provide reference clock jitter attenuation, and to

support the complex PLL multiplication ratios needed for video rate

conversion. The second stage is a FemtoClock™ frequency

multiplier that provides the low jitter, high frequency video output

clock.

Preset multiplication ratios are selected from internal lookup tables

using device input selection pins. The multiplication ratios are

optimized to support most common video rates used in professional

video system applications. The VCXO requires the use of an

external, inexpensive pullable crystal. Two crystal connections are

provided (pin selectable) so that both 60 and 59.94 base frame rates

can be supported. The VCXO requires external passive loop filter

components which are used to set the PLL loop bandwidth and

damping characteristics.

特性 Features

• Jitter attenuation and frequency translation of video clock signals

• Supports SMPTE 292M, ITU-R Rec. 601/656 and

MPEG-transport clocks

• Support of High-Definition (HD) and Standard-Definition (SD)

pixel rates

• Dual VCXO-PLL supports both 60 and 59.94Hz base frame rates

in one device

• Supports both 1000/1001 and 1001/1000 rate conversions

• Dual PLL mode for high-frequency clock generation (36MHz to

148.5MHz)

• VCXO-PLL mode for low-frequency clock generation (27MHz and

26.973MHz)

• One LVCMOS/LVTTL clock output

• Two selectable LVCMOS/LVTTL clock inputs

• LVCMOS/LVTTL compatible control signals

• RMS phase jitter @148.3516MHz, (12kHz - 20MHz):

1.089ps (typical)

• 3.3V supply voltage

• 0°C to 70°C ambient operating temperature

• Available in lead-free (RoHS 6) packages