74VCX16374数据手册集成电路（IC）的触发器规格书PDF

描述 Description

The 74VCX16374 is an advanced performance, non-inverting 16-bit D-type flip-flop. It is designed for very high-speed, very low-power operation in 1.8V, 2.5V or 3.3V systems. The VCX16374 is byte controlled, with each byte functioning identically, but independently. Each byte has separate Output Enable and Clock Pulse inputs. These control pins can be tied together for full 16-bit operation. When operating at 2.5V (or 1.8V) the part is designed to tolerate voltages it may encounter on either inputs or outputs when interfacing to 3.3V busses. It is guaranteed to be over-voltage tolerant to 3.6V. The 74VCX16374 consists of 16 edge-triggered flip-flops with individual D-type inputs and 3.6V-tolerant 3-state outputs. The clocks (CPn) and Output Enables (OEn)bar are common to all flip-flops within the respective byte. The flip-flops will store the state of individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the OEbar LOW, the contents of the flip-flops are available at the outputs. When the OEbar is HIGH, the outputs go to the high impedance state. The OEbar input level does not affect the operation of the flip-flops.

特性 Features

• Designed for Low Voltage Operation: VCC = 1.65-3.6V
• 3.6V Tolerant Inputs and Outputs
• High Speed Operation: 3.0ns max for 3.0 to 3.6V3.9ns max for 2.3 to 2.7V7.8ns max for 1.65 to 1.95V
• Static Drive: +/-24mA Drive at 3.0V+/-18mA Drive at 2.3V+/-6mA Drive at 1.65V
• Supports Live Insertion and Withdrawal
• IOFF Specification Guarantees High Impedance When VCC = 0V
• Near Zero Static Supply Current in All Three Logic States (20mA)Substantially Reduces System Power Requirements
• Latchup Performance Exceeds +/-250mA @ 125°C
• ESD Performance: Human Body Model >2000V; Machine Model >200V
• All Devices in Package TSSOP are Inherently Pb-Free

简介

74VCX16374属于集成电路（IC）的触发器。由制造生产的74VCX16374触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。