74VCX16373数据手册集成电路（IC）的锁存器规格书PDF

描述 Description

The 74VCX16373 is an advanced performance, non-inverting 16-bit transparent latch. It is designed for very high-speed, very low-power operation in 1.8V, 2.5V or 3.3V systems. The VCX16373 is byte controlled, with each byte functioning identically, but independently. Each byte has separate Output Enable and Latch Enable inputs. These control pins can be tied together for full 16-bit operation. When operating at 2.5V (or 1.8V) the part is designed to tolerate voltages it may encounter on either inputs or outputs when interfacing to 3.3V busses. It is guaranteed to be over-voltage tolerant to 3.6V. The 74VCX16373 contains 16 D-type latches with 3-state 3.6V-tolerant outputs. When the Latch Enable (LEn) inputs are HIGH, data on the Dn inputs enters the latches. In this condition, the latches are transparent, (a latch output will change state each time its D input changes). When LE is LOW, the latch stores the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-state outputs are controlled by the Output Enable (OEn)bar inputs. When OEbar is LOW, the outputs are enabled. When OEbar is HIGH, the standard outputs are in the high impedance state, but this does not interfere with new data entering into the latches.

特性 Features

• Designed for Low Voltage Operation: VCC = 1.65-3.6V
• 3.6V Tolerant Inputs and Outputs
• High Speed Operation: 3.0ns max for 3.0 to 3.6V3.9ns max for 2.3 to 2.7V6.8ns max for 1.65 to 1.95V
• Static Drive: +/-24mA Drive at 3.0V+/-18mA Drive at 2.3V+/-6mA Drive at 1.65V
• Supports Live Insertion and Withdrawal
• IOFF Specification Guarantees High Impedance When VCC = 0V
• Near Zero Static Supply Current in All Three Logic States (20mA)Substantially Reduces System Power Requirements
• Latchup Performance Exceeds +/-250mA @ 125°C
• ESD Performance: Human Body Model >2000V; Machine Model >200V
• All Devices in Package TSSOP are Inherently Pb-Free

简介

74VCX16373属于集成电路（IC）的锁存器。由制造生产的74VCX16373锁存器锁存器是类似于触发器的基本数字存储设备，但是不同之处在于，在锁存使能（或类似命名）信号处于有效逻辑状态的任何时间，保持的逻辑状态都可以改变。“透明”锁存器还允许设备输出在锁存使能信号有效时反映输入的当前状态，而相反的是，状态仅在保持状态已固定时改变。