74LVT573PW数据手册集成电路（IC）的锁存器规格书PDF

描述 Description

The 74LVT573 is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device is an octal transparent latch coupled to eight 3-state output buffers. The two sections of the device are controlled independently by Latch Enable (LE) and Output Enable (OE) control gates. The 74LVT573 has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors.
The data on the Dn inputs are transferred to the latch outputs when the Latch Enable (LE) input is High. The latch remains transparent to the data inputs while LE is High, and stores the data that is present one setup time before the High-to-Low enable transition.
The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all eight 3-state buffers independent of the latch operation.
When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in the High-impedance “OFF” state, which means they will neither drive nor load the bus.

特性 Features

• Inputs and outputs arranged for easy interfacing to microprocessors
• 3-state outputs for bus interfacing
• Common output enable control
• TTL input and output switching levels
• Input and output interface capability to systems at 5 V supply
• Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
• Live insertion and extraction permitted
• No bus current loading when output is tied to 5 V bus
• Power-up reset
• Power-up 3-state
• Latch-up protection
• JESD78 class II exceeds 500 mA

• ESD protection:
• HBM JESD22-A114E exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V

• Specified from -40 °C to +85 °C