74LVC240数据手册集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF

描述 Description

The 74LVC240A is a high performance, inverting octal buffer operating from a 1.2 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5 V allows 74LVC240A inputs to be safely driven from 5 V devices. The 74LVC240A is suitable for memory address driving and all TTL level bus oriented transceiver applications.Current drive capability is 24mA at the outputs. The Output Enable(OEbar) input, when HIGH, disables the outputs by placing them in a HIGH Z condition.

特性 Features

Designed for 1.2 V to 3.6 V VCC Operation
5 V Tolerant − Interface Capability With 5 V TTL Logic
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0 V
24 mA Output Sink and Source Capability
Near Zero Static Supply Current in All Three Logic States (10 µA) Substantially Reduces System Power Requirements
Latchup Performance Exceeds 250 mA
ESD Performance: Human Body Model >2000 V; Machine Model >200 V
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant

简介

74LVC240属于集成电路（IC）的缓冲器驱动器接收器收发器。由制造生产的74LVC240缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。