1. General description

The 74LVC1G240 is a 1-bit inverting buffer/line driver with 3-state output. The device features

an output enable OE. A HIGH on OE causes the output to assume a high-impedance OFF-state.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices

as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

2. Features and benefits

• Wide supply voltage range from 1.65 V to 5.5 V

• High noise immunity

• Complies with JEDEC standard:

• JESD8-7 (1.65 V to 1.95 V)

• JESD8-5 (2.3 V to 2.7 V)

• JESD8-B/JESD36 (2.7 V to 3.6 V)

• ±24 mA output drive (VCC = 3.0 V)

• ESD protection:

• • HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2000 V

• CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 1000 V

• CMOS low power consumption

• Inputs accept voltages up to 5 V

• Latch-up performance exceeds 250 mA

• Direct interface with TTL levels

• Specified from -40 °C to +85 °C and -40 °C to +125 °C

74LVC1G240属于集成电路（IC） > 缓冲器，驱动器，接收器，收发器。安世半导体(中国)有限公司制造生产的74LVC1G240缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。