74LV595PW中文资料8-bit serial-in/serial-out or parallel-out shift register; 3-state数据手册Nexperia规格书

描述 Description

The 74LV595 is an 8 stage serial shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. It is a low-voltage Si-gate CMOS device and is pin and functionally compatible with the 74HC595 and 74HCT595.
Data is shifted on the positive-going transitions of the SHCP input. The data in the shift register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial output (Q7S) for cascading the device. It is also provided with an asynchronous reset input MR (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW.

特性 Features

• Optimized for low voltage applications: 1.0 V to 3.6 V
• Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
• Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C
• Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 °C
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
• Has a shift register with direct clear
• Multiple package options
• Output capability:
• Parallel outputs; bus driver
• serial output; standard

• ESD protection:
• HBM JESD22-A114E exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V

应用 Application

• Serial-to-parallel data conversion
• Remote control holding register