12-stage binary ripple counter

DESCRIPTION The 74LV4040 is a low–voltage Si–gate CMOS device and is pin and function compatible with 74HC/HCT4040. FEATURES • Optimized for Low Voltage applications: 1.0 to 5.5V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Typical VOLP (output ground bounce)  0.8V @ VCC =

文件：133.75 Kbytes 页数：14 Pages

PHI

PHI

12-stage binary ripple counter

DESCRIPTION The 74LV4040 is a low–voltage Si–gate CMOS device and is pin and function compatible with 74HC/HCT4040. FEATURES • Optimized for Low Voltage applications: 1.0 to 5.5V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Typical VOLP (output ground bounce)  0.8V @ VCC =

文件：133.75 Kbytes 页数：14 Pages

PHI

PHI

12-stage Binary Counter

Description The HD74LV4040A is a 12 stage counter. This device is incremented on the falling edge (negative transition) of the input clock, and all its output is reset to a low level by applying a logical high on its reset input. Low-voltage and high-speed operation is suitable for the battery-po

文件：185.88 Kbytes 页数：11 Pages

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12-stage Binary Counter

Description The HD74LV4040A is a 12 stage counter. This device is incremented on the falling edge (negative transition) of the input clock, and all its output is reset to a low level by applying a logical high on its reset input. Low-voltage and high-speed operation is suitable for the battery-po

文件：95.44 Kbytes 页数：17 Pages

HITACHIHitachi Semiconductor

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12-stage Binary Counter

Description The HD74LV4040A is a 12 stage counter. This device is incremented on the falling edge (negative transition) of the input clock, and all its output is reset to a low level by applying a logical high on its reset input. Low-voltage and high-speed operation is suitable for the battery-po

文件：185.88 Kbytes 页数：11 Pages

RENESAS

瑞萨