Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra

文件：53.28 Kbytes 页数：5 Pages

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

Dual J-K Flip-Flops(with Clear)

Dual J-K Flip-Flops(with Clear)

文件：66.99 Kbytes 页数：6 Pages

HitachiHitachi Semiconductor

日立日立公司

DUAL J-K FLIP-FLOPS WITH CLEAR

文件：206.08 Kbytes 页数：13 Pages

TI

德州仪器

Dual J-K Flip-Flops(with Clear)

HITACHI

日立