74LS280中文资料安森美半导体数据手册PDF规格书

The SN74LS280 is a Universal 9-Bit Parity Generator/Checker. It features odd/even outputs to facilitate either odd or even parity. By cascading, the word length is easily expanded. The LS280 is designed without the expander input implementation, but the corresponding function is provided by an input at Pin 4 and the absence of any connection at Pin 3. This design permits the LS280 to be substituted for the LS180 which results in improved performance. The LS280 has buffered inputs to lower the drive requirements to one LS unit load.

• Generates Either Odd or Even Parity for Nine Data Lines

• Typical Data-to-Output Delay of only 33 ns

• Cascadable for n-Bits

• Can Be Used To Upgrade Systems Using MSI Parity Circuits

• Typical Power Dissipation = 80 mW