LOW POWER SCHOTTKY

LOW POWER SCHOTTKY The SN74LS109A consists of two high speed completely independent transition clocked JKflip-flops.

文件：96.07 Kbytes 页数：4 Pages

ONSEMI

安森美半导体

丝印：74LS109A；Package：SOP；DUAL JK POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

Package Options Include Plastic “Small Outline’ Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description These devices contain two independent J-K positive- edge triggered flip-flops. A low level

文件：378.65 Kbytes 页数：12 Pages

TI

德州仪器

丝印：74LS109A；Package：SOP；DUAL JK POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

Package Options Include Plastic “Small Outline’ Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description These devices contain two independent J-K positive- edge triggered flip-flops. A low level

文件：378.65 Kbytes 页数：12 Pages

TI

德州仪器

Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition t

文件：52.33 Kbytes 页数：5 Pages

Fairchild

仙童半导体

Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs

文件：135 Kbytes 页数：6 Pages

NSC

国半

Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition t

文件：52.33 Kbytes 页数：5 Pages

Fairchild

仙童半导体