8-Bit Serial-Input/Parallel-Output Shift Register

This 8-bit shift register features gated serial inputs and an asynchronous reset. The gated serial inputs (A and B) permit complete control over incoming data as a low at either (or both) input(s) inhibits entry of the new data and resets the first flip flop to the low level at the next clock puls

文件：36.46 Kbytes 页数：4 Pages

SLS

Low Power Schottky Logic

Features Aysnchronous Master Reset Gated Serial Data Input Fully Synchronous Data Transfers Direct drop-in replacement for obsolete components in long term programs. Industrial temperature range.

文件：333.58 Kbytes 页数：5 Pages

SS

Low Power Schottky Logic

Features Aysnchronous Master Reset Gated Serial Data Input Fully Synchronous Data Transfers Direct drop-in replacement for obsolete components in long term programs. Industrial temperature range.

文件：333.58 Kbytes 页数：5 Pages

SS

8-Bit Parallel In/Serial Output Shift Registers

General Description This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked. Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shift/load input. These registers also featur

文件：151.32 Kbytes 页数：6 Pages

SOLIDSTATE

8-Bit Parallel In/Serial Output Shift Registers

General Description This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked. Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shift/load input. These registers also featur

文件：151.29 Kbytes 页数：6 Pages

SYC

8-Bit Parallel In/Serial Output Shift Registers

General Description This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked. Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shift/load input. These registers also feature

文件：73.31 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

8-BIT SHIFT REGISTERS

The SN54L/74LS166 is an 8-Bit Shift Register. Designed with all inputs buffered, the drive requirements are lowered to one 54/74LS standard load. By utilizing input clamping diodes, switching transients are minimized and system design simplified. The LS166 is a parallel-in or serial-in, serial-

文件：106.68 Kbytes 页数：4 Pages

MOTOROLA

摩托罗拉

BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS

The SN54 /74LS168 and SN54 /74LS169 are fully synchronous 4-stage up/down counters featuring a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. The SN54 /74LS168 counts in a BCD decade (8, 4, 2, 1) sequence, whil

文件：272.36 Kbytes 页数：8 Pages

MOTOROLA

摩托罗拉

BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS

BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS The SN54/74LS168 and SN54/74LS169 are fully synchronous 4-stage up/down counters featuring a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. The S

文件：117.94 Kbytes 页数：6 Pages

ONSEMI

安森美半导体

BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS

The SN54 /74LS168 and SN54 /74LS169 are fully synchronous 4-stage up/down counters featuring a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. The SN54 /74LS168 counts in a BCD decade (8, 4, 2, 1) sequence, whil

文件：272.36 Kbytes 页数：8 Pages

MOTOROLA

摩托罗拉