74HCT4020PW数据手册集成电路（IC）的计数器除法器规格书PDF

描述 Description

The 74HT4020; 74HCT4020 is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0, and Q3 to Q13). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

特性 Features

• Wide supply voltage range from 2.0 V to 6.0 V
• Input levels:
• For 74HC4020: CMOS level
• For 74HCT4020: TTL level

• Multiple package options
• Complies with JEDEC standard no. 7A
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

应用 Application

• Frequency dividing circuits
• Time delay circuits
• Control counters