74HCT4017D-Q100数据手册集成电路（IC）的计数器除法器规格书PDF

描述 Description

The 74HC4017-Q100; 74HCT4017-Q100 is a 5-stage Johnson decade counter with 10 decoded outputs (Q0 to Q9). It has an output from the most significant flip-flop (Q5-9), two clock inputs (CP0 and CP1) and an overriding asynchronous master reset input (MR). Either a LOW-to-HIGH transition at CP0 while CP1 is LOW, or a HIGH-to-LOW transition at CP1 while CP0 is HIGH, advances the counter. The Q5-9 output is LOW while the counter is in states 5, 6, 7, 8 and 9. When cascading counters, it can be used to drive the CP0 input of the next counter. A HIGH on MR resets the counter to zero (Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW) independent of the clock inputs (CP0 and CP1). An internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses provides automatic code correction of the counter. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

特性 Features

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from ‑40 °C to +85 °C and from ‑40 °C to +125 °C

• Wide supply voltage range from 2.0 V to 6.0 V
• Input levels:
• For 74HC4017-Q100: CMOS level
• For 74HCT4017-Q100: TTL level

• Complies with JEDEC standard no. 7 A
• ESD protection:
• MIL-STD-883, method 3015 exceeds 2000 V
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

• Multiple package options