Presettable synchronous BCD decade counter; asynchronous reset

GENERAL DESCRIPTION The 74HC/HCT160 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Synchronous counting and loading • Two count enable inputs for n-bit cascading • Positive

文件：63.72 Kbytes 页数：9 Pages

PHI

PHI

SYNCHRONOUS PRESETTABLE 4-BIT COUNTER

DESCRIPTION M54/74HCT160 Decade, Asynchronous Clear M54/74HCT161 Binary, Asynchronous Clear M54/74HCT162 Decade, Synchronous Clear M54/74HCT163 Binary, Synchronous Clear The M54/74HCT160, 161, 162 and 163 are high speed CMOS SYNCHRONOUS PRESETTABLE COUNTERS fabricated with silicon gate C2MOS

文件：329.16 Kbytes 页数：16 Pages

STMICROELECTRONICS

意法半导体

Presettable synchronous BCD decade counter; asynchronous reset

GENERAL DESCRIPTION The 74HC/HCT160 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Synchronous counting and loading • Two count enable inputs for n-bit cascading • Positive

文件：63.72 Kbytes 页数：9 Pages

PHI

PHI

Presettable synchronous BCD decade counter; asynchronous reset

GENERAL DESCRIPTION The 74HC/HCT160 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Synchronous counting and loading • Two count enable inputs for n-bit cascading • Positive

文件：63.72 Kbytes 页数：9 Pages

PHI

PHI

Presettable synchronous BCD decade counter; asynchronous reset

GENERAL DESCRIPTION The 74HC/HCT160 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Synchronous counting and loading • Two count enable inputs for n-bit cascading • Positive

文件：63.72 Kbytes 页数：9 Pages

PHI

PHI