74HC594BQ-Q100中文资料8-bit shift register with output register数据手册Nexperia规格书

描述 Description

The 74HC594-Q100; 74HCT594-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register. Separate clock and reset inputs are provided on both shift and storage registers. The device features a serial input (DS) and a serial output (Q7S) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the SHCP input, and the data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. A LOW level on one of the two register reset pins (SHR and STR) will clear the corresponding register. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

特性 Features

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

• Synchronous serial input and output
• 8-bit parallel output
• Shift and storage registers have independent direct clear and clocks
• Independent clocks for shift and storage registers
• 100 MHz (typical)
• Wide supply voltage range from 2.0 V to 6.0 V
• CMOS low power dissipation
• High noise immunity
• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
• Input levels:
• For 74HC594-Q100: CMOS level
• For 74HCT594-Q100: TTL level

• Complies with JEDEC standards
• JESD8C (2.7 V to 3.6 V)
• JESD7A (2.0 V to 6.0 V)

• ESD protection:
• MIL-STD-883, method 3015 exceeds 2 kV
• HBM JESD22-A114F exceeds 2 kV
• MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

应用 Application

• Serial-to parallel data conversion
• Remote control holding register