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74HC574PW-Q100数据手册集成电路(IC)的触发器规格书PDF

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厂商型号

74HC574PW-Q100

参数属性

74HC574PW-Q100 封装/外壳为20-TSSOP(0.173",4.40mm 宽);包装为卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带;类别为集成电路(IC)的触发器;产品描述:IC FF D-TYPE SNGL 8BIT 20TSSOP

功能描述

Octal D-type flip-flop; positive edge-trigger; 3-state

封装外壳

20-TSSOP(0.173",4.40mm 宽)

制造商

Nexperia Nexperia B.V. All rights reserved

中文名称

安世 安世半导体(中国)有限公司

数据手册

下载地址下载地址二

更新时间

2025-8-8 23:00:00

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74HC574PW-Q100规格书详情

描述 Description

The 74HC574-Q100; 74HCT574-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.
The 74HC574-Q100; 74HCT574-Q100 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The 8 flip-flops store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

特性 Features

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

• 3-state non-inverting outputs for bus-oriented applications
• 8-bit positive, edge-triggered register
• Common 3-state output enable input
• ESD protection:
• MIL-STD-883, method 3015 exceeds 2000 V
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

• Multiple package options

技术参数

  • 制造商编号

    :74HC574PW-Q100

  • 生产厂家

    :Nexperia

  • VCC (V)

    :2.0 - 6.0

  • Logic switching levels

    :CMOS

  • Output drive capability (mA)

    :± 7.8

  • tpd (ns)

    :14

  • fmax (MHz)

    :133

  • Power dissipation considerations

    :low

  • Tamb (°C)

    :-40~125

  • Rth(j-a) (K/W)

    :100

  • Ψth(j-top) (K/W)

    :4.6

  • Rth(j-c) (K/W)

    :44.9

  • Package name

    :TSSOP20

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恩XP
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