74HC574BQ中文资料安世数据手册PDF规格书

1. General description

The 74HC574; 74HCT574 is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs.

The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state

of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH

clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state.

Operation of the OE input does not affect the state of the flip-flops. Inputs include clamp diodes.

This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

2. Features and benefits

• Wide supply voltage range from 2.0 V to 6.0 V

• CMOS low power dissipation

• High noise immunity

• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

• Complies with JEDEC standards:

• JESD8C (2.7 V to 3.6 V)

• JESD7A (2.0 V to 6.0 V)

• Input levels:

• For 74HC574: CMOS level

• For 74HCT574: TTL level

• 3-state non-inverting outputs for bus oriented applications

• 8-bit positive, edge-triggered register

• Common 3-state output enable input

• ESD protection:

• • HBM JESD22-A114F exceeds 2 kV

• MM JESD22-A115-A exceeds 200 V

• Specified from -40 °C to +85 °C and from -40 °C to +125 °C