Quad bilateral switches

GENERAL DESCRIPTION The 74HC/HCT4316 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Low “ON” resistance: 160Ω(typ.) at VCC−VEE= 4.5 V 120Ω(typ.) at VCC−VEE= 6.0 V 80Ω(typ.) at VCC−VEE= 9.0 V • Logic level translation: to enable 5

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Quad bilateral switches

GENERAL DESCRIPTION The 74HC/HCT4316 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Low “ON” resistance: 160Ω(typ.) at VCC−VEE= 4.5 V 120Ω(typ.) at VCC−VEE= 6.0 V 80Ω(typ.) at VCC−VEE= 9.0 V • Logic level translation: to enable 5

文件：130.669 Kbytes 页数：15 Pages

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Quad single-pole single-throw analog switch

1. General description The 74HC4316; 74HCT4316 is a quad single pole, single throw analog switch (SPST). Each switch features two input/output terminals (nY and nZ) and an active HIGH enable input (nS). When nS is LOW, the analog switch is turned off. When E is HIGH all four analog switches are

文件：327.94 Kbytes 页数：23 Pages

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安世

Quad single-pole single-throw analog switch

1. General description The 74HC4316; 74HCT4316 is a quad single pole, single throw analog switch (SPST). Each switch features two input/output terminals (nY and nZ) and an active HIGH enable input (nS). When nS is LOW, the analog switch is turned off. When E is HIGH all four analog switches are

文件：327.94 Kbytes 页数：23 Pages

NEXPERIA

安世

Quad bilateral switches

GENERAL DESCRIPTION The 74HC/HCT4316 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Low “ON” resistance: 160Ω(typ.) at VCC−VEE= 4.5 V 120Ω(typ.) at VCC−VEE= 6.0 V 80Ω(typ.) at VCC−VEE= 9.0 V • Logic level translation: to enable 5

文件：130.669 Kbytes 页数：15 Pages

PHI

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