74HC280D数据手册集成电路（IC）的奇偶校验发生器校验器规格书PDF

描述 Description

The 74HC280; 74HCT280 is a 9-bit parity generator or checker. Both even and odd parity outputs are available. The even parity output (PE) is HIGH when an even number of data inputs (I0 to I8) is HIGH. The odd parity output (PO) is HIGH when an odd number of data inputs are HIGH. Expansion to larger word sizes is accomplished by tying the even outputs (PE) of up to nine parallel devices to the final stage data inputs. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC

特性 Features

• Complies with JEDEC standard no. 7A
• Input levels:
• For 74HC280: CMOS level
• For 74HCT280: TTL level

• Word-length easily expanded by cascading
• Generates either odd or even parity for nine data bits
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V

• Specified from -40 °C to +85 °C and -40 °C to +125 °C