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74HC163PW数据手册集成电路(IC)的计数器除法器规格书PDF

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厂商型号

74HC163PW

参数属性

74HC163PW 封装/外壳为16-TSSOP(0.173",4.40mm 宽);包装为管件;类别为集成电路(IC)的计数器除法器;产品描述:IC SYNC 4BIT BINAR COUNT 16TSSOP

功能描述

Presettable synchronous 4-bit binary counter; synchronous reset

封装外壳

16-TSSOP(0.173",4.40mm 宽)

制造商

Nexperia Nexperia B.V. All rights reserved

中文名称

安世 安世半导体(中国)有限公司

数据手册

下载地址下载地址二

更新时间

2025-8-8 17:24:00

人工找货

74HC163PW价格和库存,欢迎联系客服免费人工找货

74HC163PW规格书详情

描述 Description

The 74HC163; 74HCT163 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action. It causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW after the next positive-going transition on the clock input (CP). This action occurs regardless of the levels at input pins PE, CET and CEP. This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate. The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
The CP to TC propagation delay and CEP to CP set-up time determine the maximum clock frequency for the cascaded counters according to the following formula:
fmax= / (tP (max)(CP to TC) + tSU(CEP to CP) )

特性 Features

• Complies with JEDEC standard no. 7A
• Input levels:
• For 74HC163: CMOS level
• For 74HCT163: TTL level

• Synchronous counting and loading
• 2 count enable inputs for n-bit cascading
• Synchronous reset
• Positive-edge triggered clock
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V

• Multiple package options
• Specified from ‑40 °C to +85 °C and ‑40 °C to +125 °C

应用 Application

• Television sets
• Home-sound sets
• Multimedia systems
• All mains fed audio systems
• Car audio (boosters)

技术参数

  • 制造商编号

    :74HC163PW

  • 生产厂家

    :Nexperia

  • Product status

    :Production

  • V_CC (V)

    :2.0 - 6.0

  • Output drive capability (mA)

    :+/- 5.2

  • Logic switching levels

    :CMOS

  • t_pd (ns)

    :17

  • Power dissipation considerations

    :low

  • T_amb (Cel)

    :-40~125

  • R_th(j-a) (K/W)

    :116

  • Ψ_th(j-top) (K/W)

    :2.5

  • R_th(j-c) (K/W)

    :44.7

  • Package name

    :TSSOP16

供应商 型号 品牌 批号 封装 库存 备注 价格
恩XP
21+
TSSOP16
1773
原装现货假一赔十
询价
TI
1815+
TSSOP16
6528
只做原装正品现货!或订货,假一赔十!
询价
PHI
23+
8486
原厂授权代理,海外优势订货渠道。可提供大量库存,详
询价
ti
24+
N/A
6980
原装现货,可开13%税票
询价
PHI
23+
TSSOP
12300
询价
Nexperia/安世
22+
SOT403-1
72000
原厂原装正品现货
询价
Nexperia
25+
电联咨询
7800
公司现货,提供拆样技术支持
询价
Nexperia USA Inc.
24+
16-TSSOP
56200
一级代理/放心采购
询价
24+
5000
公司存货
询价
NEXPERIA/安世
24+
原厂原封可拆样
65258
百分百原装现货,实单必成
询价