74F652集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF中文资料

General Description

These devices consist of bus transceiver circuits with D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function.

特性 Features

■ Independent registers for A and B buses

■ Multiplexed real-time and stored data

■ 74F652 non-inverting data path