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型号	下载订购	功能描述	制造商上传企业	LOGO
74F533SJMX	文件：166.3 Kbytes Page：8 Pages	Octal Transparent Latch with TRI-STATE Outputs 文件：166.3 Kbytes 页数：8 Pages	NSC 国半	NSC
74F533SMQB	文件：166.3 Kbytes Page：8 Pages	Octal Transparent Latch with TRI-STATE Outputs 文件：166.3 Kbytes 页数：8 Pages	NSC 国半	NSC
74F533SMX	文件：166.3 Kbytes Page：8 Pages	Octal Transparent Latch with TRI-STATE Outputs 文件：166.3 Kbytes 页数：8 Pages	NSC 国半	NSC
74F533	文件：166.3 Kbytes Page：8 Pages	Octal Transparent Latch with TRI-STATE Outputs 文件：166.3 Kbytes 页数：8 Pages	NSC 国半	NSC
74F533	文件：97.3 Kbytes Page：12 Pages	Latch/flip-flop DESCRIPTION The 74F533 is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled independently by Enable (E) and Output Enable (OE) control gates. FEATURES • 8-bit positive edge-triggered register – 74F534 • 3-State inverting output bu 文件：97.3 Kbytes 页数：12 Pages	PHI PHI	PHI
74F533	文件：80.4 Kbytes Page：7 Pages	Octal Transparent Latch with 3-STATE Outputs General Description The 74F533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Outpu 文件：80.4 Kbytes 页数：7 Pages	FAIRCHILD 仙童半导体	FAIRCHILD

更多74F533SJMX供应商更新时间2026-1-23 16:01:00