Quad D flip-flop

DESCRIPTION The 74F175A is a quad, edge-triggered D-type flip-flop with individual D inputs and both Q and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. FEATURES • Four edge-triggered D-type flip-flops • B

文件：82.25 Kbytes 页数：10 Pages

PHI

PHI

Quad D flip-flop

DESCRIPTION The 74F175A is a quad, edge-triggered D-type flip-flop with individual D inputs and both Q and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. FEATURES • Four edge-triggered D-type flip-flops • B

文件：82.25 Kbytes 页数：10 Pages

PHI

PHI

Quad D flip-flop

DESCRIPTION The 74F175A is a quad, edge-triggered D-type flip-flop with individual D inputs and both Q and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. FEATURES • Four edge-triggered D-type flip-flops • B

文件：82.25 Kbytes 页数：10 Pages

PHI

PHI

Quad D flip-flop

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Quad D flip-flop

DESCRIPTION\nThe 74F175A is a quad, edge-triggered D-type flip-flop with individual D inputs and both Q and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, on • Four edge-triggered D-type flip-flops\n• Buffered common clock\n• Buffered asynchronous Master Reset\n• True and complementary outputs\n• Industrial temperature range available (–40°C to +85°C)\n• PNP light loading inputs;

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