Quad D-Type Flip-Flop

General Description The 74F175 is a high-speed quad D-type flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each fli

文件：80.45 Kbytes 页数：7 Pages

FAIRCHILD

仙童半导体

QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR

文件：359.72 Kbytes 页数：12 Pages

TI

德州仪器

Quad D-Type Flip-Flop

General Description\nThe 74F175 is a high-speed quad D-type flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition.\nBoth true and complemented outputs of each flip- ■ Edge-triggered D-type inputs\n■ Buffered positive edge-triggered clock\n■ Asynchronous common reset\n■ True and complement output;

ONSEMI

安森美半导体

丝印：74F175；Package：SOP；QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR

Contains Four Flip-Flops With Double-Rail Outputs Buffered Clock and Direct Clear Inputs Applications Include: – Buffer/Storage Registers – Shift Registers – Pattern Generators description This positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic

文件：572.1 Kbytes 页数：16 Pages

TI

德州仪器

丝印：74F175；Package：SOP；QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR

Contains Four Flip-Flops With Double-Rail Outputs Buffered Clock and Direct Clear Inputs Applications Include: – Buffer/Storage Registers – Shift Registers – Pattern Generators description This positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic

文件：572.1 Kbytes 页数：16 Pages

TI

德州仪器

Quad D flip-flop

DESCRIPTION The 74F175A is a quad, edge-triggered D-type flip-flop with individual D inputs and both Q and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. FEATURES • Four edge-triggered D-type flip-flops • B

文件：82.25 Kbytes 页数：10 Pages

PHI

PHI

Quad D flip-flop

DESCRIPTION The 74F175A is a quad, edge-triggered D-type flip-flop with individual D inputs and both Q and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. FEATURES • Four edge-triggered D-type flip-flops • B

文件：82.25 Kbytes 页数：10 Pages

PHI

PHI

Quad D flip-flop

DESCRIPTION The 74F175A is a quad, edge-triggered D-type flip-flop with individual D inputs and both Q and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. FEATURES • Four edge-triggered D-type flip-flops • B

文件：82.25 Kbytes 页数：10 Pages

PHI

PHI

Quad D-Type Flip-Flop

General Description The 74F175 is a high-speed quad D-type flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each fli

文件：80.45 Kbytes 页数：7 Pages

FAIRCHILD

仙童半导体

Quad D-Type Flip-Flop

General Description The 74F175 is a high-speed quad D-type flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each fli

文件：80.45 Kbytes 页数：7 Pages

FAIRCHILD

仙童半导体