1. General description

The 74AVC2T45 is a dual-bit, dual-supply transceiver that enables bidirectional level translation.

It features two data input-output ports (nA and nB), a direction control input (DIR) and dual-supply

pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V

and 3.6 V making the device suitable for translating between any of the low voltage nodes

(0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins nA and DIR are referenced to VCC(A) and pins nB

are referenced to VCC(B). A HIGH on DIR allows transmission from nA to nB and a LOW on DIR

allows transmission from nB to nA.

The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry

disables the output, preventing any damaging backflow current through the device when it is

powered down. In Suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B are

in the high-impedance OFF-state.

2. Features and benefits

• Wide supply voltage range:

• VCC(A): 0.8 V to 3.6 V

• VCC(B): 0.8 V to 3.6 V

• High noise immunity

• Complies with JEDEC standards:

• JESD8-12 (0.8 V to 1.3 V)

• JESD8-11 (0.9 V to 1.65 V)

• JESD8-7 (1.2 V to 1.95 V)

• JESD8-5 (1.8 V to 2.7 V)

• JESD8-B (2.7 V to 3.6 V)

• ESD protection:

• HBM JESD22-A114F Class 3B exceeds 8000 V

• MM JESD22-A115-A exceeds 200 V

• CDM JESD22-C101C exceeds 1000 V

• Maximum data rates:

• 500 Mbit/s (1.8 V to 3.3 V translation)

• 320 Mbit/s (<1.8 V to 3.3 V translation)

• 320 Mbit/s (translate to 2.5 V or 1.8 V)

• 280 Mbit/s (translate to 1.5 V)

• 240 Mbit/s (translate to 1.2 V)

• Suspend mode

• Latch-up performance exceeds 100 mA per JESD 78 Class II

• Inputs accept voltages up to 3.6 V

• Low noise overshoot and undershoot < 10 of VCC

• IOFF circuitry provides partial Power-down mode operation

• Multiple package options

• Specified from -40 °C to +85 °C and -40 °C to +125 °C

74AVC2T45GT属于集成电路（IC） > 转换器，电平移位器。安世半导体(中国)有限公司制造生产的74AVC2T45GT转换器，电平移位器逻辑转换器或电平移位器 IC 可用于在数字逻辑设备之间传递信息，这些设备可在不同/不兼容的供电电压下工作，或可实现不同的信令方式。例如，可以将需要 5 V 电源的数字输出传感器连接到具有 3.3 V I/O 电源的 FPGA，或者在 CMOS 或 TTL 等单端信令方式与 PECL 或 LVDS 等差分技术之间进行转换。