Low-power dual D-type flip-flop; positive-edge trigger

The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition for predictable operation.\

Nexperia

安世

Low-power dual D-type flip-flop; positive-edge trigger

文件：111.99 Kbytes 页数：20 Pages

恩XP

Package：8-XFDFN；包装：卷带（TR） 功能：标准 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE DUAL 1BIT 8XSON

Nexperia USA Inc.

Low-power dual D-type flip-flop; positive-edge trigger

文件：94.62 Kbytes 页数：18 Pages

PHI

PHI