Package：8-XFDFN；包装：卷带（TR）剪切带（CT） 功能：标准 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE DUAL 1BIT 8XSON

Nexperia USA Inc.

Low-power dual D-type flip-flop; positive-edge trigger

1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock

文件：279.06 Kbytes 页数：19 Pages

NEXPERIA

安世

Low-power dual D-type flip-flop; positive-edge trigger

1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock

文件：279.06 Kbytes 页数：19 Pages

NEXPERIA

安世

Low-power dual D-type flip-flop; positive-edge trigger

1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock

文件：279.06 Kbytes 页数：19 Pages

NEXPERIA

安世

Low-power dual D-type flip-flop; positive-edge trigger

1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock

文件：279.06 Kbytes 页数：19 Pages

NEXPERIA

安世