74AUP1G79GF数据手册集成电路（IC）的触发器规格书PDF

描述 Description

Low-power D-type flip-flop; positive-edge trigger - The 74AUP1G79 provides the single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one setup time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

特性 Features

·Wide supply voltage range from 0.8 V to 3.6 V
·High noise immunity
·Complies with JEDEC standards: ·JESD8-12 (0.8 V to 1.3 V)
·JESD8-11 (0.9 V to 1.65 V)
·JESD8-7 (1.2 V to 1.95 V)
·JESD8-5 (1.8 V to 2.7 V)
·JESD8-B (2.7 V to 3.6 V)