74AUP1G17GS数据手册集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF

描述 Description

The 74AUP1G17 provides the single Schmitt-trigger buffer. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.

特性 Features

• Wide supply voltage range from 0.8 V to 3.6 V
• High noise immunity
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 5000 V
• CDM: ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 1000 V
• MM: JESD22-A115-A exceeds 200 V

• Low static power consumption; ICC = 0.9 μA (maximum)
• Latch-up performance exceeds 100 mA per JESD 78 Class II
• Inputs accept voltages up to 3.6 V
• Low noise overshoot and undershoot < 10 % of VCC
• IOFF circuitry provides partial Power-down mode operation
• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C