74ALVC16244数据手册集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF

描述 Description

The 74ALVC16244 is an advanced performance, non-inverting 16-bit buffer. It is designed for very hgigh-speed, very low-power operation in 1.8 V, 2.5 V or 3.3 V systems. The 74ALVC16244 is nibble controlled with each nibble functioning identically, but independently.The control pins may be tied together to obtain full 16-bit operation. The 3-state outputs are controlled by an Output Enable (OEnbar) input for each nibble. When (OEnbar) is LOW, the outputs are on.When the (OEnbar) is HIGH, the outputs are in the high impedance state.

特性 Features

• Designed for Low Voltage Operation: VCC = 1.65-3.6 V
• 3.6 V Tolerant Inputs and Outputs
• High Speed Operation
• Static Drive
• Supports Live Insertion and Withdrawal
• IOFF Specification Guarantees High Impledance When VCC = 0 V
• Near Zero Static Supply Current in All Three Logic States (40 µA)
• Latchup Performance Exceeds ± 250 mA @ 125 °C
• ESD Performance: Human Body Model ≥ 2000 V; Machine Model ≥ 200 V
• Second Source to Industry Standard 74ALVC16244

简介

74ALVC16244属于集成电路（IC）的缓冲器驱动器接收器收发器。由制造生产的74ALVC16244缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。