Dual D-type flip-flop with set and reset

DESCRIPTION The 74ALS74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock input. When set and reset

文件：50.48 Kbytes 页数：10 Pages

PHI

PHI

Dual D-type flip-flop with set and reset

DESCRIPTION The 74ALS74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock input. When set and reset

文件：50.48 Kbytes 页数：10 Pages

PHI

PHI

Dual D-type flip-flop with set and reset

DESCRIPTION The 74ALS74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock input. When set and reset

文件：50.48 Kbytes 页数：10 Pages

PHI

PHI

Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear

General Description The DM74ALS74A contains two independent positive edge-triggered flip-flops. Each flip-flop has individual D, clock, clear and preset inputs, and also complementary Q and Q outputs. Information at input D is transferred to the Q output on the positive going edge of the clock p

文件：68.98 Kbytes 页数：7 Pages

FAIRCHILD

仙童半导体

Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear

General Description The DM74ALS74A contains two independent positive edge-triggered flip-flops. Each flip-flop has individual D, clock, clear and preset inputs, and also complementary Q and Q outputs. Information at input D is transferred to the Q output on the positive going edge of the clock p

文件：68.98 Kbytes 页数：7 Pages

FAIRCHILD

仙童半导体