Latch/flip-flop

DESCRIPTION The 74ALS373 is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates. The data on the D inputs is transferred to the latch outputs when the enable (E) inp

文件：144.77 Kbytes 页数：13 Pages

PHI

PHI

Latch/flip-flop

DESCRIPTION The 74ALS373 is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates. The data on the D inputs is transferred to the latch outputs when the enable (E) inp

文件：144.77 Kbytes 页数：13 Pages

PHI

PHI

Latch/flip-flop

DESCRIPTION The 74ALS373 is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates. The data on the D inputs is transferred to the latch outputs when the enable (E) inp

文件：144.77 Kbytes 页数：13 Pages

PHI

PHI

Latch/flip-flop

DESCRIPTION The 74ALS373 is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates. The data on the D inputs is transferred to the latch outputs when the enable (E) inp

文件：144.77 Kbytes 页数：13 Pages

PHI

PHI

Latch/flip-flop

DESCRIPTION The 74ALS373 is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates. The data on the D inputs is transferred to the latch outputs when the enable (E) inp

文件：144.77 Kbytes 页数：13 Pages

PHI

PHI

Latch/flip-flop

DESCRIPTION The 74ALS373 is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates. The data on the D inputs is transferred to the latch outputs when the enable (E) inp

文件：144.77 Kbytes 页数：13 Pages

PHI

PHI

Latch/flip-flop

DESCRIPTION The 74ALS373 is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates. The data on the D inputs is transferred to the latch outputs when the enable (E) inp

文件：144.77 Kbytes 页数：13 Pages

PHI

PHI

Latch/flip-flop

DESCRIPTION The 74ALS373 is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates. The data on the D inputs is transferred to the latch outputs when the enable (E) inp

文件：144.77 Kbytes 页数：13 Pages

PHI

PHI

Octal D flip-flop with enable

DESCRIPTION The 74ALS377 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) is Low. The register is fully edge-triggered. The state of each D input, one setup time before

文件：122.47 Kbytes 页数：10 Pages

PHI

PHI

Octal D flip-flop with enable

DESCRIPTION The 74ALS377 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) is Low. The register is fully edge-triggered. The state of each D input, one setup time before

文件：122.47 Kbytes 页数：10 Pages

PHI

PHI