Octal D-type flip-flop

DESCRIPTION The 74ALS273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup tim

文件：114.54 Kbytes 页数：9 Pages

PHI

PHI

Octal D-type flip-flop

DESCRIPTION The 74ALS273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup tim

文件：114.54 Kbytes 页数：9 Pages

PHI

PHI

Octal D-type flip-flop

DESCRIPTION The 74ALS273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup tim

文件：114.54 Kbytes 页数：9 Pages

PHI

PHI

Octal D-Type Edge-Triggered Flip-Flop with Clear

General Description These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input. Information at the D inputs meeting the setup requirements is transferred to the Q outputs on the positive-going edge of the clock pul

文件：76.76 Kbytes 页数：7 Pages

FAIRCHILD

仙童半导体

Octal D-Type Edge-Triggered Flip-Flop with Clear

General Description These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input. Information at the D inputs meeting the setup requirements is transferred to the Q outputs on the positive-going edge of the clock pulse.

文件：183.6 Kbytes 页数：9 Pages

ONSEMI

安森美半导体