74AHCT377PW数据手册集成电路（IC）的触发器规格书PDF

描述 Description

The 74AHC377; 74AHCT377 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.
The 74AHC377; 74AHCT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common clock input (CP) loads all flip-flops simultaneously when the data enable input (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. The E input is only required to be stable one set-up time prior to the LOW-to-HIGH transition for predictable operation.
For versions associated with the 74AHC377; 74AHCT377, refer to the following:
For the master reset version, see 74AHC273; 74AHCT273For the transparent latch version, see 74AHC373; 74AHCT373For the 3-state version, see 74AHC374; 74AHCT374

特性 Features

• Balanced propagation delays
• All inputs have Schmitt-trigger actions
• Inputs accept voltages higher than VCC
• Ideal for addressable register applications
• Data enable for address and data synchronization
• Eight positive-edge triggered D-type flip-flops
• Input levels:
• For 74AHC377: CMOS level
• For 74AHCT377: TTL level

• ESD protection:
• HBM EIA/JESD22-A114E exceeds 2000 V
• MM EIA/JESD22-A115-A exceeds 200 V
• CDM EIA/JESD22-C101C exceeds 1000 V

• Multiple package options
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C