1. General description

The 74AHC273; 74AHCT273 is a high-speed Si-gate CMOS device and is pin compatible with

Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.

The 74AHC273; 74AHCT273 has eight edge-triggered, D-type flip-flops with individual D inputs

and Q outputs. The common clock (CP) and master reset (MR) inputs, load and reset (clear) all

flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock

transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced

LOW, independent of clock or data inputs, by a LOW on the MR input.

The device is useful for applications where only the true output is required and the clock and

master reset are common to all storage elements.

2. Features

• Balanced propagation delays

• All inputs have Schmitt-trigger actions

• Inputs accept voltages higher than VCC

• Ideal buffer for MOS microcontroller or memory

• Common clock and master reset

• Input levels:

• For 74AHC273: CMOS level

• For 74AHCT273: TTL level

• ESD protection:

• HBM JESD22-A114E exceeds 2000 V

• MM JESD22-A115-A exceeds 200 V

• CDM JESD22-C101C exceeds 1000 V

• Multiple package options

• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

74AHC273PW属于集成电路（IC） > 触发器。安世半导体(中国)有限公司制造生产的74AHC273PW触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。