74AHC259D中文资料恩XP数据手册PDF规格书

General description

The 74AHC259; 74AHCT259 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.

Features

■ Balanced propagation delays

■ All inputs have Schmitt-trigger actions

■ Combines demultiplexer and 8-bit latch

■ Serial-to-parallel capability

■ Output from each storage bit available

■ Random (addressable) data entry

■ Easily expandable

■ Common reset input

■ Useful as a 3-to-8 active HIGH decoder

■ Inputs accept voltages higher than VCC

■ Input levels:

◆ For 74AHC259: CMOS level

◆ For 74AHCT259: TTL level

■ ESD protection:

◆ HBM EIA/JESD22-A114E exceeds 2000 V

◆ MM EIA/JESD22-A115-A exceeds 200 V

◆ CDM EIA/JESD22-C101C exceeds 1000 V

■ Multiple package options

■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C