74AHC126PW数据手册集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF

描述 Description

The 74AHC126; 74AHCT126 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.
The 74AHC126; 74AHCT126 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A LOW-level at pin nOE causes the outputs to assume a high-impedance OFF-state.
The 74AHC126; 74AHCT126 is identical to the 74AHC125; 74AHCT125 but has active HIGH output enable inputs.

特性 Features

• Balanced propagation delays
• All inputs have Schmitt-trigger action
• Inputs accept voltages higher than VCC
• Input levels:
• For 74AHC126: CMOS level
• For 74AHCT126: TTL level

• ESD protection:
• HBM JESD22-A114E exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V
• CDM JESD22-C101C exceeds 1000 V

• Multiple package options
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C