Octal D-Type Flip-Flop with Clock Enable

General Description The AC/ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one

文件：113.73 Kbytes 页数：9 Pages

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

Octal D-Type Flip-Flop with Clock Enable

General Description The AC/ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one

文件：113.73 Kbytes 页数：9 Pages

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

Octal D-Type Flip-Flop with Clock Enable

文件：426.64 Kbytes 页数：13 Pages

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

Octal D-Type Flip-Flop with Clock Enable

General Description The AC/ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one

文件：113.73 Kbytes 页数：9 Pages

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司