74AC11240DBR.A中文资料德州仪器数据手册PDF规格书

Flow-Through Architecture Optimizes

PCB Layout

Center-Pin VCC and GND Configurations

Minimize High-Speed Switching Noise

EPIC (Enhanced-Performance Implanted

CMOS) 1-
m Process

500-mA Typical Latch-Up Immunity at

125°C

Package Options Include Plastic

Small-Outline (DW) and Shrink

Small-Outline (DB) Packages, and Standard

Plastic 300-mil DIPs (NT)

description

This octal buffer/line driver is designed specifically

to improve both the performance and density of

3-state memory address drivers, clock drivers,

and bus-oriented receivers and transmitters. This

device provides inverting outputs and

symmetrical active-low output-enable (OE)

inputs. This device features high fan-out and

improved fan-in.

The 74AC11240 is organized as two 4-bit buffers/line drivers with separate OE inputs. When OE is low, the

device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the

high-impedance state.

The 74AC11240 is characterized for operation from –40°C to 85°C.