72V293中文资料64K x 18 / 128K x 9 SuperSync II FIFO, 3.3V数据手册Renesas规格书

描述 Description

The 72V293 128K x 9/64K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.

特性 Features

Functionally compatible with the 72V255/65/75/85 SuperSync FIFOs
Up to 166 MHz Operation of the Clocks
User selectable Asynchronous read and/or write ports (BGA Only)
User selectable input and output port bus sizing
Pin to Pin compatible to the higher density 72V2x3/72V21x3 devices
5V tolerant inputs
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Easily expandable in depth and width
JTAG port, provided for Boundary Scan function (BGA Only)
Independent Read and Write Clocks
Available in 80-pin TQFP or 100-pin BGA packages
Industrial temperature range (–40C to +85C) is available