72V265中文资料16K x 18 SuperSync FIFO, 3.3V数据手册Renesas规格书

描述 Description

The 72V265 is an 16K x 18 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72265 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data.

特性 Features

Pin-compatible with the 72V2x5 SuperSync FIFOs
Functionally compatible with the 5 Volt 722x5 family
10ns read/write cycle time (6.5ns access time)
Fixed, low first word data latency time
5V input tolerant
Auto power down minimizes standby power consumption
Retransmit operation with fixed, low first word data latency time
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, Easily expandable in depth and width
Independent Read and Write clocks (permit reading and writing simultaneously)
Available in 64-pin TQFP and STQFP packages
Industrial temperature range (–40C to +85C) is available