256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 150MHz (3.8ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (

文件：313.82 Kbytes 页数：27 Pages

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3.3V 512K x 18 ZBT Synchronous 3.3V I/O PipeLined SRAM

The 71V65803 3.3VCMOS SRAM organized as 512K X 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65803 contains data I/O, address and control signal registe High performance system speed - 150MHz (3.8ns Clock-to-Data Access)\n ZBTTM Feature - No dead cycles between write and read cycles\n Internally synchronized output buffer enable eliminates the need to control OE\n Single R/W (READ/WRITE) control pin\n Positive clock-edge triggered address, data, and;

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256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 150MHz (3.8ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (

文件：313.82 Kbytes 页数：27 Pages

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256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 150MHz (3.8ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (

文件：313.82 Kbytes 页数：27 Pages

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 150MHz (3.8ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (

文件：313.82 Kbytes 页数：27 Pages

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 150MHz (3.8ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (

文件：313.82 Kbytes 页数：27 Pages

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 150MHz (3.8ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (

文件：313.82 Kbytes 页数：27 Pages

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 150MHz (3.8ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (

文件：313.82 Kbytes 页数：27 Pages

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 150MHz (3.8ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (

文件：313.82 Kbytes 页数：27 Pages

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 150MHz (3.8ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (

文件：313.82 Kbytes 页数：27 Pages

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